Troubleshoot

Debugging generate statement

/* The `ifdef SYNTHESIS is mandatory.

The $display() task does not affect the netlist but causes additional

messages to be written out during elaboration. */

module test #(N=32) (

output [N-1:0] out,

input [N-1:0] in

);

genvar I;

generate

for (I = $left(out); I >= $right(out); I--) begin:GEN

`ifdef SYNTHESIS

always $display("Instantiating: mod GEN[%d].inst ( .out(out[%d]),

.in(in[%d]) )", I, I, I);

`endif

mod inst( .out(out[I]), .in(in[I]) );

end:GEN

endgenerate

endmodule:test