RDC

RDC issues

RDC refers to paths where a async reset on a flop can generate metastability in the circuit.

There are few scenarios this can happen.

1. Launch and capture flop are in same (or different) clock domain, but async reset to them are in different domain.

2. Launch flop has an async reset, but capture flop is reset less flop.

Possible solutions

1. Reset ordering

Ensure "rst2" is asserted prior or with "rst1". This will ensure no metastability on FF2.

2. Add a guard signal for path between FF1 and FF2.

A synchronized guard signal. This signal can ensure the async signal won't propagate.

3. Add a synchronizer cell between FF1 and FF2.

The sync cell ensures async signal won't propagate. But it also adds latency.

4. Add a clock gate in the receive domain.

By turning off the clock on receiving domain, the async signal on reset assertion will not be sampled.

RDC can also exist when a Flop with async reset is connected to a resetless flop.

The above solutions can be explored here too

• If the Q-pin of the flop is always "0" (reset value) prior to the assertion of async-reset. Then it doesn't cause any RDC violation. In this case, the following constraint is added to ignore the path.

create_rdc_static -from FF/Q -from_reset rst