SYNTHESIS

Using stub in synthesis

dc_shell> set_app_var hdlin_sv_blackbox_modules design_list

dc_shell> set_app_var hdlin_sv_interface_only_modules design_list


e.g.:

dc_shell> set_app_var hdlin_sv_blackbox_modules {mod1 mod2}

dc_shell> set_app_var hdlin_sv_interface_only_modules {mod1 mod2}

hdlin_sv_blackbox_modules

The hdlin_sv_blackbox_modules variable has been in the tool since the X-2005.09 release. It works by completely ignoring the RTL for modules in the list, leaving a hole in the RTL. The resulting link and unresolved reference warnings are suppressed.

With this method, the port information for the ignored modules is missing completely. As a result,

  • The module ports have names inferred from the reference (instantiation), which might be incorrect.

  • The module ports have an assumed direction of inout, which can cause a variety of issues.

Because the module content is ignored completely, this method ignores any syntax errors in the module header.

hdlin_sv_interface_only_modules

The hdlin_sv_interface_only_modules variable was introduced in the N-2017.09 release. It works by reading only the port information inside the module and ignoring the design content up to the endmodule statement. (The design content is ignored completely, not read in and then removed.)

With this method,

  • The black-box module ports have the correct names.

  • The black-box module ports have the correct directions.

  • The module header and port information must be syntactically correct.

Libraries used in Design compiler


Technology library: Contains the information about the characteristics of each

cell, such as cell names, pin names, area, delay arcs, and pin loading. It also

contains the function and design rule constraints of each cell. Technology

libraries are also characterized for internal power and leakage power.


Symbol library: Contains the definitions of the graphic symbols that represent

library cells in the design schematics. Symbol libraries are used to display

synthesis results graphically in Design Vision. Design Compiler uses the symbol

library to generate the design schematic.


DesignWare library: Contains reusable building blocks or components such as

adders, multipliers, and so on. These are technology independent. That is, they

are not mapped to a specific technology library.

The standard synthetic library, standard.sldb, implements basic components such

as adders, multipliers, subtractors, comparators, and so on. You do not need to

specify the standard synthetic library, standard.sldb. Design Compiler

automatically uses this library.

The DesignWare Foundation library, dw_foundation.sldb, contains all the basic

components with additional faster implementations, such as vector adders, Wallace

tree multipliers, ASIC debugger, JTAG, FIFO and RAMS, and so on. To use the

DesignWare Foundation, you must have a separate DesignWare license.


DesignWare minPower, dw_minpower.sldb, is a synthetic library. To use the

DesignWare minPower technology, you need a separate DesignWare-LP license.


Generic technology (GTECH) library: Consists of basic logic gates and flip-flops.

GTECH libraries are technology independent. That is, they are not mapped to a

specific technology library. GTECH libraries contain 89 library cells, and the

functionality is defined for each cell.


Milkyway reference library: Design Compiler in topographical mode needs the

Milkyway reference library, which contains the physical representation of standard

cells and macros. The Milkyway reference library also defines the width and height

of the smallest placeable instance and the routing directions.