AXI Pipe delay

Vinayaka's Notes:

• Parameter type will support custom data type like struct.

module axi_pipe #(

//parameter type DT = logic

parameter int unsigned DT = 32

)

(

output logic [DT-1:0] data_o,

output logic data_o_val,

input logic data_o_rdy,

input logic [DT-1:0] data_i,

input logic data_i_val,

output logic data_i_rdy,

input logic clk,

input logic rstn

);

// Data register on incoming val-rdy

always_ff @(posedge clk, negedge rstn) begin

if (!rstn)

data_o <= '0;

else if (data_i_val && data_i_rdy)

data_o <= data_i;

end

// Generate output valid

always_ff @(posedge clk, negedge rstn) begin

if (!rstn)

data_o_val <= '0;

else if (data_i_val && data_i_rdy)

data_o_val <= '1;

else if (data_o_rdy)

data_o_val <= '0;

end

// Generate ready for incoming data

assign data_i_rdy = ~(data_o_val && ~data_o_rdy);

endmodule