edge detector

module edge_dep (

input logic data,

output logic pos,

output logic neg,

input logic clk,

input logic rstn

);

logic data_r1;

always_ff @(posedge clk, negedge rstn) begin

if (!rstn) begin

data_r1 <= '0;

end else begin

data_r1 <= data;

end

end

// Posedge pulse

assign pos = data && ~data_r1;

// Negedge pulse

assign neg = ~data && data_r1;

endmodule

module tb_edge_dep;

logic data;

logic pos;

logic neg;

logic clk;

logic rstn;

edge_dep u_inst (.*);

initial begin

clk = '0;

rstn = '0;

fork

begin

forever

clk = #5 ~clk;

end

begin

repeat(10) @(posedge clk);

rstn = '1;

end

join

end

initial begin

data = '0;

#200;

@(posedge clk);

data = #1 '1;

repeat(10) @(posedge clk);

data = #1 '0;

repeat(10) @(posedge clk);

data = #1 '1;

repeat(10) @(posedge clk);

#100;

$finish;

end

initial begin

$dumpfile("dump.vcd");

$dumpvars;

end

endmodule