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ctags
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ASIC
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Flip flop
Capacitor basics
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System verilog
Structs, unions & Enum
Macros
RTL tips and tricks
Issues
CDC
REPORTS
RESET
Implementaion ideas
Basic Link list
Pseudo Random Number Generator
AXI Pipe delay
Programmable pipe delay
Reset issue - struct with enums
Bit hacks
SYNTHESIS
Standard components
edge detector
RDC
VC Spyglass - RDC
Others
GIT
My Resume
My Scripts
ASIC SQUAD
Home
PERL
PERL General
PERL Regex Tips
PERL Hash
PERL Modules
PERL Command line
Python - WIP
Basic construct
Text editor
VIM
useful shortcuts
vimrc - basic
vimrc - my current
custom vim functions
vimdiff
vimconf
CtrlP
ctags
SHELL
CSH
BASH
AWK
SED
Xterm
EDA
Conformal LEC
nCompare - Verdi
Coretools
VCS
DC - Synthesis
Troubleshoot
ASIC
Basic
Flip flop
Capacitor basics
FSM
Timing constraints
System verilog
Structs, unions & Enum
Macros
RTL tips and tricks
Issues
CDC
REPORTS
RESET
Implementaion ideas
Basic Link list
Pseudo Random Number Generator
AXI Pipe delay
Programmable pipe delay
Reset issue - struct with enums
Bit hacks
SYNTHESIS
Standard components
edge detector
RDC
VC Spyglass - RDC
Others
GIT
My Resume
My Scripts
More
Home
PERL
PERL General
PERL Regex Tips
PERL Hash
PERL Modules
PERL Command line
Python - WIP
Basic construct
Text editor
VIM
useful shortcuts
vimrc - basic
vimrc - my current
custom vim functions
vimdiff
vimconf
CtrlP
ctags
SHELL
CSH
BASH
AWK
SED
Xterm
EDA
Conformal LEC
nCompare - Verdi
Coretools
VCS
DC - Synthesis
Troubleshoot
ASIC
Basic
Flip flop
Capacitor basics
FSM
Timing constraints
System verilog
Structs, unions & Enum
Macros
RTL tips and tricks
Issues
CDC
REPORTS
RESET
Implementaion ideas
Basic Link list
Pseudo Random Number Generator
AXI Pipe delay
Programmable pipe delay
Reset issue - struct with enums
Bit hacks
SYNTHESIS
Standard components
edge detector
RDC
VC Spyglass - RDC
Others
GIT
My Resume
My Scripts
Capacitor
Basic
Capacitor_basics.pdf
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Capacitor_basics.pdf